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85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 1 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer 0 1 0 1 loop0 loop1 g eneral d escription the ICS85454-01 is a 2:1/1:2 multiplexer and a member of the hiperclocks tm family of high performance clock solutions from ics. the 2:1 multiplexer allows one of 2 inputs to be select- ed onto one output pin and the 1:2 mux switches one input to both of two outputs. this device may be useful for multiplexing multi-rate ethernet phys which have 100mbit and 1000mbit transmit/receive pairs onto an optical sfp module which has a single transmit/receive pair. another mode allows loop back testing and allows the output of a phy transmit pair to be routed to the phy input pair. for examples, please refer to the application information section of the data sheet. the ICS85454-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5ghz. the device is packaged in a small, 3mm x 3mm vfqfn package, making it ideal for use on space-constrained boards. f eatures ? dual 2:1/1:2 mux ? three lvds outputs ? three differential inputs ? differential inputs can accept the following differential levels: lvpecl, lvds, cml ? loopback test mode available ? maximum output frequency: 2.5ghz ? part-to-part skew: 250ps (maximum) ? additive phase jitter, rms: 0.05ps (typical) ? propagation delay: 550ps (maximum) ? 2.5v operating supply ? -40c to 85c ambient operating temperature ? available in both standard and lead-free rohs compliant packages b lock d iagram p in a ssignment hiperclocks? ic s ICS85454-01 16-lead vfqfn 3mm x 3mm x 0.95 package body k package top view qa0 nqa0 qa1 nqa1 ina0 nina0 ina1 nina1 inb ninb selb gnd qb nqb sela v dd 1 2 3 4 12 11 10 9 5 6 7 8 16 15 14 13 inb ninb qb nqb ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 sela selb
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 2 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer t able 1. p in d escriptions t able 2. p in c haracteristics t able 3. i nput c ontrol f unction t able s t u p n i l o r t n o c e d o m a l e sb l e s 00 d e t c e l e s 0 p o o l 10 d e t c e l e s 1 p o o l 01 0 p o o l : e d o m k c a b p o o l 11 1 p o o l : e d o m k c a b p o o l r e b m u ne m a ne p y tn o i t p i r c s e d 2 , 10 a q n , 0 a qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 4 , 31 a q n , 1 a qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 5b n it u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 6b n i nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 7b l e st u p n in w o d l l u p r o f d e s u s t u p n i e m a s s t c e l e s , h g i h n e h w . s t u p t u o x a q r o f n i p t c e l e s . t u p n i b n i s t c e l e s , w o l n e h w . t u p t u o b q . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8d n gr e w o p. d n u o r g y l p p u s r e w o p 91 a n i nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 0 11 a n it u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 1 10 a n i nt u p n i / p u l l u p n w o d l l u p v . t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i d d . g n i t a o l f t f e l n e h w t l u a f e d 2 / 2 10 a n it u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 3 1v d d r e w o p. n i p y l p p u s e v i t i s o p 4 1a l e st u p n in w o d l l u p . t u p n i 1 a n i s t c e l e s , h g i h n e h w . s t u p t u o b q r o f n i p t c e l e s . s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i 0 a n i s t c e l e s , w o l n e h w 6 1 , 5 1b q , b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 5 . 7 3k ? r p u l l u p r o t s i s e r p u l l u p t u p n i 5 . 7 3k ?
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 3 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer t able 4a. p ower s upply dc c haracteristics , v dd = 2.5v 5% a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current 10ma surge current 15ma operating temperature range , ta -40c to +85c storage temperature, t stg -65c to 150c package thermal impedance, ja 51.5c/w (0 lfpm) (junction-to-ambient) note: stresses beyond those listed under absolute maximum ratings may cause permanent damage t o the device. these ratings are stress specifi- cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect product reliability. l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i 7 . 1v d d 3 . 0 +v v l i e g a t l o v w o l t u p n i 07 . 0v i h i t n e r r u c h g i h t u p n ib l e s , a l e sv d d v = n i v 5 2 6 . 2 =0 5 1a i l i t n e r r u c w o l t u p n ib l e s , a l e sv d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a t able 4b. lvcmos / lvttl dc c haracteristics , v dd = 2.5v 5% t able 4c. d ifferential dc c haracteristics , v dd = 2.5v 5% l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e v i t i s o p 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 0 9a m l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m i h i t n e r r u c h g i h t u p n i b n i , x a n i b n i n , x a n i n 0 5 10 5 10 5 1a i l i t n e r r u c w o l t u p n i b n i , x a n i b n i n , x a n i n 0 5 1 -0 5 1 -0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 02 . 15 1 . 02 . 15 1 . 02 . 1v v r m c ; e g a t l o v t u p n i e d o m d n o m m o c 2 , 1 e t o n 2 . 1v d d 2 . 1v d d 2 . 1v d d v v s a d e n i f e d s i e g a t l o v t u p n i e d o m n o m m o c : 1 e t o n h i . v s i b n i n , b n i d n a x a n i n , x a n i r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n d d . v 3 . 0 +
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 4 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer t able 5. ac c haracteristics , v dd = 2.375v to 2.625v t able 4d. lvds dc c haracteristics , v dd = 2.5v 5% l o b m y sr e t e m a r a ps n o i t i d n o cm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 5 . 2z h g t d p 1 e t o n ; y a l e d n o i t a g a p o r p x a q o t b n i r o b q o t x a n i0 5 20 5 5s p x a q o t x a n i0 0 30 5 6s p t ) p p ( k s3 , 2 e t o n ; w e k s t r a p - o t - t r a p 0 5 2s p t t i j ; s m r , r e t t i j e s a h p e v i t i d d a r e f f u b n o i t c e s r e t t i j e s a h p e v i t i d d a o t r e f e r , z h m 8 0 . 2 2 6 = ? z h m 0 2 - z h k 2 1 5 0 . 0s p x u m n o i t a l o s i n o i t a l o s i x u mt u p t u o z h m 0 0 5 @5 5b d t r /t f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 50 5 2s p d e r u s a e m e r a s r e t e m a r a p l l a . d e t o n e s i w r e h t o s s e l n u z h g 7 . 1 . t n i o p g n i s s o r c t u p t u o l a i t n e r e f f i d e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n s e g a t l o v y l p p u s e m a s e h t t a g n i t a r e p o s e c i v e d t n e r e f f i d n o s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n d e r u s a e m e r a s t u p t u o e h t , e c i v e d h c a e n o s t u p n i f o e p y t e m a s e h t g n i s u . s n o i t i d n o c d a o l l a u q e h t i w d n a . s t n i o p s s o r c l a i t n e r e f f i d e h t t a . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 3 e t o n l o b m y sr e t e m a r a p c 0 4 -c 5 2c 5 8 s t i n u n i mp y tx a mn i mp y tx a mn i mp y tx a m v d o e g a t l o v t u p t u o l a i t n e r e f f i d0 5 20 5 30 5 40 5 20 5 30 5 40 5 20 5 30 5 4v m ? v d o v d o e g n a h c e d u t i n g a m0 30 30 3v m v s o e g a t l o v t e s f f o3 9 . 08 1 . 13 4 . 17 9 . 02 2 . 17 4 . 12 0 . 17 2 . 12 5 . 1v ? v s o v s o e g n a h c e d u t i n g a m0 10 10 1v m . m a r g a i d " t i u c r i c t s e t d a o l t u p t u o v 5 . 2 " , n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p o t r e f e r : 1 e t o n
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 5 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer a dditive p hase j itter additive phase jitter at 622.08mhz (12khz - 20mhz) = 0.05ps (typical) 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 10 100 1k 10k 100k 1m 10m 100m the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a as with most timing specifications, phase noise measure- ments have issues. the primary issue relates to the limita- tions of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated ratio of the power in the 1hz band to the power in the funda- mental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the fre- quency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependant on the input source and measurement equipment. o ffset f rom c arrier f requency (h z ) ssb p hase n oise dbc/h z
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 6 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer o utput l oad ac t est c ircuit d ifferential i nput l evel p ropagation d elay p art - to -p art s kew o utput r ise /f all t ime v cmr cross points v pp gnd nina0, nina1 ninb v dd ina0, ina1 inb t sk(pp) nqx qx nqy qy pa rt 1 pa rt 2 clock outputs 20% 80% 80% 20% t r t f v sw i n g t pd nina0, nina1 ninb qa0, qa1, qb nqa0, nqa1, nqb ina0, ina1 inb p arameter m easurement i nformation scope qx nqx lv d s 2.5v5% power supply +- float gnd d ifferential o utput v oltage o ffset v oltage s etup out out lv d s dc input ? ? ? v os / v os v dd ? ? ? 100 out out lv d s dc input v od / v od v dd
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 7 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer a pplication i nformation figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels should be located as close as possible to the input pin. the ratio of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. v_ref r1 1k c1 0.1u r2 1k single ended clock input in nin vdd i nputs : in/nin i nput : for applications not requiring the use of the differential input, both in and nin can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from in to ground. lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lv d s all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached.
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 8 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer d ifferential c lock i nput i nterface the in/nin accepts lv pecl, cml, sstl and other differen- tial signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 2a to 2d show interface ex- amples for the hiperclocks in/nin input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termi- nation requirements. f igure 2a. h i p er c lock s in/nin i nput d riven by an o pen c ollector cml d river f igure 2b. h i p er c lock s in/nin i nput d riven by a b uilt -i n p ullup cml d river f igure 2c. h i p er c lock s in/nin i nput d riven by a 3.3v lvpecl d river f igure 2d. h i p er c lock s in/nin i nput d riven by a 3.3v lvds d river zo = 50 ohm r2 50 3.3v hiperclocks in nin 3.3v 3.3v cml zo = 50 ohm r1 50 r1 100 3.3v hiperclocks in nin 3.3v zo = 50 ohm zo = 50 ohm cml built-in pull-up 3.3v hiperclocks in nin r1 100 3.3v lvds zo = 50 ohm zo = 50 ohm 3.3v 3.3v hiperclocks in nin r1 100 lvds zo = 50 ohm zo = 50 ohm
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 9 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer t ypical a pplication d iagram for h ost b us a dapter b oards for r outing b etween i nternal and e xternal c onnectors serdes 0 1 ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 inb ninb qb nqb external connector protocol controller pci bus internal connector 0 1 sela selb host adapter board
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 10 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer f igure 3. t ypical lvds d river t ermination 2.5v lvds d river t ermination figure 3 shows a typical termination for lvds driver in characteristic impedance of 100 ? differential (50 ? single) 2.5v 100 ohm differential transmission line 2.5v lvds_driv er r1 100 + - 100 ? ? ? ? ? differential transmission line transmission line environment. for buffer with multiple ldvs driver, it is recommended to terminate the unused outputs. t ypical a pplication d iagram for h ot -s wappable l inks to r edundant s witch f abric c ards serdes 0 1 ina0 nina0 qa0 nqa0 ina1 nina1 qa1 nqa1 inb ninb qb nqb loop 0 loop 1 0 1 sela selb linecard tx rx #1 #0 switch fabric backplane redundant switch card
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 11 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS85454-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS85454-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. power_ max = v dd_max * i dd_max = 2.625v * 90ma = 236.3mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow of and a multi-layer board, the appropriate value is 51.5c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.236w * 51.5c/w = 97.2c. this is well below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 16-p in vfqfn, f orced c onvection ja vs. 0 air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 51. 5c/w
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 12 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer r eliability i nformation t ransistor c ount the transistor count for ICS85454-01 is: 171 t able 7. ja vs . a ir f low t able for 16 l ead vfqfn ja vs. 0 air flow (linear feet per minute) 0 multi-layer pcb, jedec standard test boards 51. 5c/w
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 13 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer p ackage o utline - k s uffix for 16 l ead vfqfn t able 8. p ackage d imensions reference document: jedec publication 95, mo-220 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y sm u m i n i mm u m i x a m n 6 1 a 0 8 . 00 . 1 1 a 05 0 . 0 3 a e c n e r e f e r 5 2 . 0 b 8 1 . 00 3 . 0 e c i s a b 0 5 . 0 n d 4 n e 4 d 0 . 3 2 d 0 . 18 . 1 e 0 . 3 2 e 0 . 18 . 1 l 0 3 . 00 5 . 0
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 14 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademark, hiperclocks is a trademark of integrated circuit systems, inc. or its subsidiaries in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t 1 0 - k a 4 5 4 5 8 s c i1 0 a 5n f q f v d a e l 6 1e b u tc 5 8 o t c 0 4 - t 1 0 - k a 4 5 4 5 8 s c i1 0 a 5n f q f v d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - f l 1 0 - k a 4 5 4 5 8 s c il 1 0 an f q f v " e e r f - d a e l " d a e l 6 1e b u tc 5 8 o t c 0 4 - t f l 1 0 - k a 4 5 4 5 8 s c il 1 0 an f q f v " e e r f - d a e l " d a e l 6 1l e e r & e p a t 0 0 5 2c 5 8 o t c 0 4 - . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
85454ak-01 www.icst.com/products/hiperclocks.html rev. b june 16, 2006 15 integrated circuit systems, inc. ICS85454-01 d ual 2:1/1:2 d ifferential - to -lvds m ultiplexer t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d b d 4 t 9 t 4 4 1 v d e g n a h c - s c i t s i r e t c a r a h c c d s d v l d o d e g n a h c . s r e t e m a r a p ? v d o v / s o . m u m i x a m o t l a c i p y t m o r f s r e t e m a r a p . e b u t o t y a r t m o r f g n i g a k c a p g n i p p i h s d e t c e r r o c - n o i t a m r o f n i g n i r e d r o 6 0 / 4 1 / 3 b8 t3 1 o t . x a m 5 2 . 1 / n i m 5 2 . 0 m o r f 2 e / 2 d d e t c e r r o c - e l b a t n o i s n e m i d e g a k c a p . x a m 8 . 1 / . n i m 0 . 1 6 0 / 6 1 / 6

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